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march 2002 copyright ? alliance semiconductor. all rights reserved. ? as7c33128pfs32a as7c33128pfs36a 3.3v 128k x 32/36 pipelin e burst synchronous sram 3/4/02; v.1.4 alliance semiconductor p. 1 of 13 features ? organization: 131,072 words 32 or 36 bits fast clock speeds to 200 mhz in lvttl/lvcmos fast clock to data acce ss: 3.0/3.1/3.5/4.0/5.0 ns fast oe access time: 3.0/3.1/3.5/4.0/5.0 ns fully synchronous register-to-register operation single register ?flow-through? mode single-cycle deselect dual-cycle deselect also available (as7c33128pfd32a/ as7c33128pfd36a) pentium? 1 compatible architecture and timing asynchronous output enable control economical 100-pin tqfp package byte write enables multiple chip enables for easy expansion 3.3 core power supply 2.5v or 3.3v i/o operation with separate v ddq 30 mw typical standby power in power down mode ntd? 1 pipeline architecture available (as7c33128ntd32a/ as7c33128ntd36a) 1pentium ? is a registered trademark of intel corporation. ntd? is a trademark of alliance semiconductor corporation. all trademarks mentioned in this document are the property of their respective owners. logic block diagram q0 q1 128k 32/36 memory array burst logic clk clr ce address dq ce clk dq d clk dq byte write registers register dq c clk dq byte write registers dq b clk dq byte write registers dq a clk dq byte write registers enable clk dq register enable clk dq delay register ce output registers input registers power down 4 36/32 17 15 17 17 gwe bwe bw d adv adsc adsp clk ce0 ce1 ce2 bw c bw b bw a oe a [16:0] zz lbo oe ft clk clk 36/32 36/32 dq [a:d] pin arrangement dqp c /nc dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c ft v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d /nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dqp b /nc dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a /nc lbo a5 a4 a3 a2 a1 a0 nc nc v ss v dd nc nc a10 a11 a12 a13 a14 a15 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a6 a7 ce0 ce1 bw d bw c bw b bw a ce2 v dd v ss clk gwe bwe oe adsc adsp adv a8 a9 nc vdd a16 note: pins 1,30,51,80 are nc for 32 tqfp 14 20 mm selection guide ?200 ?183 ?166 ?133 ?100 units minimum cycle time 5 5.4 6 7.5 10 ns maximum clock frequency 200 183 166 133 100 mhz maximum pipelined clock access time 3 3.1 3.5 4 5 ns maximum operating current 570 540 475 425 325 ma maximum standby current 160 140 130 100 90 ma maximum cmos standby current (dc) 30 30 30 30 30 ma
as7c33128pfs32a as7c33128pfs36a ? 3/4/02; v.1.4 alliance semiconductor p. 2 of 13 functional description the as7c33128pfs32a and as7c33128pfs36a are high -performance cmos 4-mbit synchronous static random acce ss memory (sram) devices organized as 131,072 words 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequenc y on any given technology. timing for these devices is co mpatible with existing pentium ? synchronous cache specifications. this architecture is suited for asic, dsp (tms320c6x), and powerpc ? 1 -based systems in computing, datacom, instru mentation, and telecommunications systems. fast cycle times of 5.0/5.4/6.0/7. 5/10 ns with clock access times (t cd ) of 3.0/3.1/3.5/4.0/5.0 ns enable 200, 183, 166, 133 and 100 mhz bus frequencies. three chip enable (ce ) inputs permit easy memory expans ion. burst operation is initiated in one of two ways: the controller address strobe (adsc ), or the processor address strobe (adsp ). the burst advance pin (adv ) allows subsequent inte rnally generated burst addresses. read cycles are initiated with adsp (regardless of we and adsc ) using the new external address cloc ked into the on-chip address register when adsp is sampled low, the chip enables are sampled active, and the output buffer is enabled with oe . in a read operation the data accessed by the current address, registered in the address registers by the positive edge of clk, are carried to the data-out registers and driven on the output pins on the next po sitive edge of clk. adv is ignored on the clock edge that samples adsp asserted, but is sampled on all subsequent clock edges. address is incremented internally for the next access of the burst when adv is sampled low, and both address strobes are high. burst mode is selectable with the lbo input. with lbo unconnected or driven high, burst operations use a pentium ? count sequence. with lbo driven low, the device uses a linear count sequence suitable for powerpc ? and many other applications. write cycles are performed by disabling the output buffers with oe and asserting a write command. a global write enable gwe writes all 32/ 36 bits regardless of the state of individual bw[a:d] inputs. alternately, when gwe is high, one or more bytes may be written by asserting bwe and the appropriate individual byte bwn signal(s). bwn is ignored on the clock edge that samples adsp low, but is sampled on all subsequent clock edges. output buffers are disabled when bwn is sampled low (regardless of oe ). data is clocked into the data input register when bwn is sampled low. address is incremented internally to the next burst address if bwn and adv are sampled low. read or write cycles may also be initiated with adsc instead of adsp . the differences between cycles initiated with adsc and adsp follow. adsp must be sampled high when adsc is sampled low to init iate a cycle with adsc . we signals are sampled on the clock edge that samples adsc low (and adsp high). master chip enable ce0 blocks adsp , but not adsc . as7c33128pfs32a and as7c33128pfs36a family opera tes from a core 3.3v power supply. i/os use a separate power supply that can op erate at 2.5v or 3.3v. these devices are avai lable in a 100-pin 14 20 mm tqfp package. x = don?t care, l = low, h = high, t = true, f = false; *= valid read; n = a, b, c, d; we , wen = internal write signal. 1powerpc ? is a trademark international business machines corporation. capacitance parameter symbol signals test conditions max unit input capacitance c in address and control pins v in = 0v 5 pf i/o capacitance c i/o i/o pins v in = v out = 0v 7 pf write enable truth table (per byte) gwe bwe bwn wen lxx t hll t hhx f* hlhf * burst order interleaved burst order lbo =1 linear burst order lbo =0 starting address 00 01 10 11 starting address 00 01 10 11 first increment 01 00 11 10 first increment 01 10 11 00 second increment 10 11 00 01 second increment 10 11 00 01 third increment 11 10 01 00 third increment 11 00 01 10
as7c33128pfs32a as7c33128pfs36a ? 3/4/02; v.1.4 alliance semiconductor p. 3 of 13 stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indica ted in the operational sections of this specification is not im plied. exposure to absolute maximum rating conditions may affect reliability. signal descriptions signal i/o properties description clk i clock clock. all inputs except oe , ft , zz, lbo are synchronous to this clock. a0?a16 i sync address. sampled when all chip enables are active and adsc or adsp are asserted. dq[a,b,c,d] i/o sync data. driven as output when the chip is enabled and oe is active. ce0 isync master chip enable. sampled on clock edges when adsp or adsc is active. when ce0 is inactive, adsp is blocked. refer to the synchronous truth table for more information. ce1, ce2 isync synchronous chip enables. active high and active low, respectively. sampled on clock edges when adsc is active or when ce0 and adsp are active. adsp isync address strobe processor. asserted low to load a new bus address or to enter standby mode. adsc i sync address strobe controller. asserted low to load a new address or to enter standby mode. adv i sync advance. asserted low to continue burst read/write. gwe isync global write enable. asserted low to write all 32/36 bits. when high, bwe and bw[a:d] control write enable. bwe i sync byte write enable. asserted low with gwe = high to enable effect of bw[a:d] inputs. bw[a,b,c,d] isync write enables. used to control write of individual bytes when gwe = high and bwe = low. if any of bw[a:d] is active with gwe = high and bwe = low the cycle is a write cycle. if all bw[a:d] are inactive the cycle is a read cycle. oe iasync asynchronous output enable. i/o pins are driven when oe is active and the chip is in read mode. lbo i static default = high count mode. when driven high, count sequence follows intel xor convention. when driven low, count sequence follows linear convention. this signal is internally pulled high. 18 ft istatic flow-through mode.when low, enables single register flow-through mode. connect to v dd if unused or for pipelined operation. zz i async sleep. places device in low power mode ; data is retained. connect to gnd if unused. absolute maximum ratings parameter symbol min max unit power supply voltage relative to gnd v dd , v ddq ?0.5 +4.6 v input voltage relative to gnd (input pins) v in ?0.5 v dd + 0.5 v input voltage relative to gnd (i/o pins) v in ?0.5 v ddq + 0.5 v power dissipation p d ?1.8w dc output current i out ?50ma storage temperature (plastic) t stg ?65 +150 o c temperature under bias t bias ?65 +135 o c
as7c33128pfs32a as7c33128pfs36a ? 3/4/02; v.1.4 alliance semiconductor p. 4 of 13 1 see ?write enable truth table? on page 2 for more information. 2 q in flow through mode. 3 for write operation following a read, oe must be high before the input data set up time and held high throughout the input hold time. key: x = don?t care, l = low, h = high. synchronous truth table ce0 ce1 ce2 adsp adsc adv wen 1 oe address accessed clk operation dq h x x x l x x x na l to h deselect hi ? z l l x l x x x x na l to h deselect hi ? z l l x h l x x x na l to h deselect hi ? z l x h l x x x x na l to h deselect hi ? z l x h h l x x x na l to h deselect hi ? z l h l l x x x l external l to h begin read hi ? z 2 l h l l x x x h external l to h begin read hi ? z lhlhlxfl external l to hbegin readhi ? z 2 lhlhlxfh external l to hbegin readhi ? z xxxhhlfl next l to hcont. read q x x x h h l f h next l to h cont. read hi ? z x x x h h h f l current l to h suspend read q x x x h h h f h current l to h suspend read hi ? z hxxxhlfl next l to hcont. read q h x x x h l f h next l to h cont. read hi ? z h x x x h h f l current l to h suspend read q h x x x h h f h current l to h suspend read hi ? z lhlhlxtx external l to hbegin writed 3 x x x h h l t x next l to h cont. write d h x x x h l t x next l to h cont. write d x x x h h h t x current l to h suspend write d h x x x h h t x current l to h suspend write d
as7c33128pfs32a as7c33128pfs36a ? 3/4/02; v.1.4 alliance semiconductor p. 5 of 13 recommended operating conditions parameter symbol min nominal max unit supply voltage v dd 3.135 3.3 3.6 v v ss 0.0 0.0 0.0 3.3v i/o supply voltage v ddq 3.135 3.3 3.6 v v ssq 0.0 0.0 0.0 2.5v i/o supply voltage v ddq 2.35 2.5 2.9 v v ssq 0.0 0.0 0.0 input voltages 1 1 input voltage ranges apply to 3.3v i/o operation. for 2. 5v i/o operation, contact factory for input specifications. address and control pins v ih 2.0 ? v dd + 0.3 v v il ?0.5 2 2 v il min. = ?2.0v for pulse width less than 0.2 t rc . ?0.8 i/o pins v ih 2.0 ? v ddq + 0.3 v v il ?0.5 2 ?0.8 ambient operating temperature t a 0?70 c tqfp thermal resistance description conditions symbol ty p i c a l units thermal resistance (junction to ambient) 1 1 this parameter is sampled. test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/ jesd51 ja 46 c/w thermal resistance (junction to top of case) 1 jc 2.8 c/w
as7c33128pfs32a as7c33128pfs36a ? 3/4/02; v.1.4 alliance semiconductor p. 6 of 13 dc electrical characteristics parameter symbol test conditions ?200 ?183 ?166 ?133 ?100 unit min max min max min max min max min max input leakage current 1 |i li |v dd = max, v in = gnd to v dd ?2?2? 2 ? 2 ? 2a output leakage current |i lo | oe v ih , v dd = max, v out = gnd to v dd ?2?2? 2 ? 2 ? 2a operating power supply current i cc 2 ce0 = v il , ce1 = v ih , ce2 = v il , f = f max , i out = 0 ma ? 570 ? 540 ? 475 ? 425 ? 325 ma standby power supply current i sb deselected, f = f max , zz v il ? 160 ? 140 ? 130 ? 100 ? 90 ma i sb1 deselected, f = 0, zz 0.2v all v in 0.2v or v dd ? 0.2v ? 30 ? 30 ? 30 ? 30 ? 30 i sb2 deselected, f = f max , zz v dd ? 0.2v all v in v il or v ih ? 30 ? 30 ? 30 ? 30 ? 30 output voltage v ol i ol = 8 ma, v ddq = 3.465v ? 0.4 ? 0.4 ? 0.4 ? 0.4 ? 0.4 v v oh i oh = ?4 ma, v ddq = 3.135v 2.4 ? 2.4 ? 2.4 ? 2.4 ? 2.4 ? 1 lbo pin has an internal pull- up and input leakage = 10 a. 2 i cc given with no output loading. i cc increases with faster cycles times and greater output loading. dc electrical characteristi cs for 2.5v i/o operation parameter symbol test conditions ?200 ?183 ?166 ?133 ?100 unit min max min max min max min max min max output leakage current |i lo | oe v ih , v dd = max, v out = gnd to v dd ?11?11?1 1 ?1 1 ?1 1 a output voltage v ol i ol = 2 ma, v ddq = 2.65v ? 0.7 ? 0.7 ? 0.7 ? 0.7 ? 0.7 v v oh i oh = ?2 ma, v ddq = 2.35v 1.7 ? 1.7 ? 1.7 ? 1.7 ? 1.7 ?
as7c33128pfs32a as7c33128pfs36a ? 3/4/02; v.1.4 alliance semiconductor p. 7 of 13 timing characteristics over operating range parameter sym ?200 ?183 ?166 ?133 ?100 unit notes 1 min max min max min max min max min max clock frequency f max ? 200 ? 183 ? 166 ? 133 ? 100 mhz cycle time (pipelined mode) t cyc 5 ? 5.4 ? 6 ? 7.5 ? 10 ? ns cycle time (flow-through mode) t cycf 9 ? 10 ? 10 ? 12 ? 12 ? ns clock access time (pipelined mode) t cd ?3.0?3.1?3.5?4.0?5.0ns clock access time (flow-through mode) t cdf ? 8.5 ? 9 ? 9 ? 10 ? 12 ns output enable low to data valid t oe ?3.0?3.1?3.5?4.0?5.0ns clock high to output low z t lzc 0?0?0?0?0?ns2,3,4 data output invalid from clock high t oh 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns 2 output enable low to output low z t lzoe 0?0?0?0?0?ns2,3,4 output enable high to output high z t hzoe ?3.0?3.1?3.5?4.0?4.5ns2,3,4 clock high to output high z t hzc ?3.0?3.1?3.5?4.0?5.0ns2,3,4 output enable high to invalid output t ohoe 0?0?0?0?0?ns clock high pulse width t ch 2.2 ? 2.4 ? 2.4 ? 2.5 ? 3.5 ? ns 5 clock low pulse width t cl 2.2 ? 2.4 ? 2.4 ? 2.5 ? 3.5 ? ns 5 address setup to clock high t as 1.4 ? 1.4 ? 1.5 ? 1.5 ? 2.0 ? ns 6 data setup to clock high t ds 1.4 ? 1.4 ? 1.5 ? 1.5 ? 2.0 ? ns 6 write setup to clock high t ws 1.4 ? 1.4 ? 1.5 ? 1.5 ? 2.0 ? ns 6,7 chip select setup to clock high t css 1.4 ? 1.4 ? 1.5 ? 1.5 ? 2.0 ? ns 6,8 address hold from clock high t ah 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6 data hold from clock high t dh 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6 write hold from clock high t wh 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6,7 chip select hold from clock high t csh 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6,8 adv setup to clock high t advs 1.4 ? 1.4 ? 1.5 ? 1.5 ? 2.0 ? ns 6 adsp setup to clock high t adsps 1.4 ? 1.4 ? 1.5 ? 1.5 ? 2.0 ? ns 6 adsc setup to clock high t adscs 1.4 ? 1.4 ? 1.5 ? 1.5 ? 2.0 ? ns 6 adv hold from clock high t advh 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6 adsp hold from clock high t adsph 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6 adsc hold from clock high t adsch 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6 1 see ?notes? on page 11.
as7c33128pfs32a as7c33128pfs36a ? 3/4/02; v.1.4 alliance semiconductor p. 8 of 13 key to switching waveforms timing waveform of read cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. bw[a:d] is don?t care. undefined/don?t care falling input rising input t cyc t ch t cl t adsps t adsph t as t ah t ws t advs t oh clk adsp adsc address gwe , bwe ce0 , ce2 adv oe d out t css t csh t hzc t cd t wh t advh t hzoe t adscs t adsch load new address adv inserts wait states q(a2y10) q(a2y11) q(a3) q(a2) q(a2y01) q(a3y01) q(a3y10) q(a1) a2 a1 a3 ce1 (pipelined mode) d out q(a2y10) q(a2y11) q(a3) q(a2y01) q(a3y01) q(a3y10) q(a3y11) q(a1) (flow-through mode) t hzc t oe t lzoe
as7c33128pfs32a as7c33128pfs36a ? 3/4/02; v.1.4 alliance semiconductor p. 9 of 13 timing waveform of write cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. t cyc t cl t adsps t adsph t adscs t adsch t as t ah t ws t wh t css t advs t ds t dh clk adsp adsc address bwe ce0 , ce2 adv oe data in t csh t advh d(a2y01) d(a2y10) d(a3) d(a2) d(a2y01) d(a3y01) d(a3y10) d(a1) d(a2y11) adv suspends burst adsc loads new address a1 a2 a3 t ch ce1 bw[a:d]
as7c33128pfs32a as7c33128pfs36a ? 3/4/02; v.1.4 alliance semiconductor p. 10 of 13 timing waveform of read/write cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. t ch t cyc t cl t adsps t adsph t as t ah t ws t wh t advs t ds t dh t oh clk adsp address gwe ce0 , ce2 adv oe d in d out t lzc t advh t lzoe t oe t cd q(a1) q(a3y01) d(a2) q(a3) q(a3y10) q(a3y11) a1 a2 a3 ce1 t hzoe (pipeline mode) d out q(a1) q(a3y01) q(a3y10) (flow-through mode) t cdf q(a3y11)
? as7c33128pfs32a as7c33128pfs36a 3/4/02; v.1.4 alliance semiconductor p. 11 of 13 ac test conditions notes 1 for test conditions, see ac test conditions , figures a, b, c. 2 this parameter measured with output load condition in figure c. 3 this parameter is sampled, but not 100% tested. 4t hzoe is less than t lzoe ; and t hzc is less than t lzc at any given temperature and voltage. 5 tch measured as high above vih and tcl measured as low below vil. 6 this is a synchronous device. all addresses must meet the specif ied setup and hold times for all rising edges of clk. all othe r synchronous inputs must meet the setup and hold times for all rising edges of clk when chip is enabled. 7 write refers to gwe , bwe , bw[a:d] . 8 chip select refers to ce0 , ce1, ce2 . z 0 = 50 ? d out 50 ? figure b: output load (a) 30 pf* figure a: input waveform 10% 90% gnd 90% 10% +3.0v output load: see figure b, except for t lzc , t lzoe , t hzoe , t hzc , see figure c. input pulse level: gnd to 3v. see figure a. input rise and fall time (measured at 0.3v and 2.7v): 2 ns. see figure a. input and output timing reference levels: 1.5v. v l = 1.5v for 3.3v i/o; = v ddq /2 for 2.5v i/o 353 ? / 1538? 5 pf* 319 ? / 1667? d out gnd figure c: output load (b) *including scope and jig capacitance thevenin equivalent: +3.3v for 3.3v i/o; /+2.5v for 2.5v i/o package dimensions 100-pin quad flat pack (tqfp) tqfp min max a1 0.05 0.15 a2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 d 13.90 14.10 e 19.90 20.10 e 0.65 nominal hd 15.90 16.10 he 21.90 22.10 l 0.45 0.75 l1 1.00 nominal 0 7 dimensions in millimeters he e hd d b e a1 a2 l1 l c
as7c33128pfs32a as7c33128pfs36a ? 3/4/02; v.1.4 alliance semiconductor p. 12 of 13
? as7c33128pfs32a as7c33128pfs36a ? copyright alliance semiconductor corporation. all rights reserved. our three-point logo, our name and intelliwatt are tradema rks or registered trademarks of alliance. all other brand and p roduct names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance?s best data and/o r estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant chan ges to these specifications are possible. the information in this p roduct data sheet is intended to be general descriptive information for potential customers and users, and is not intended to o perate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product describ ed herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchan tability, or infringement of any intellectual property rights, except as express agreed to in alliance?s terms and conditions of sale (which are available from alliance). all sales of alliance product s are made exclusively according to alliance?s terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life-supporting system s where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manu facturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. 3/4/02; v.1.4 alliance semiconductor p. 13 of 13 1.alliance semiconductor sram prefix 2.operating voltage: 33=3.3v 3.organization: 128=128k 4.pipeline-flowthrough (each device works in both modes) 5.deselect: s=single cycle deselect 6.organization: 32=x32; 36=x36 7.production version: a=first production version 8.clock speed (mhz) 9.package type: tq=tqfp 10.operating temperature: c=commercial ( 0 c to 70 c); i=industrial ( -40 c to 85 c) ordering information package width ?200 mhz ?183 mhz ?166 mhz ?133 mhz ?100 mhz tqfp x32 as7c33128pfs32a- 200tqc as7c33128pfs32a- 183tqc as7c33128pfs32a- 166tqc as7c33128pfs32a- 133tqc as7c33128pfs32a- 100tqc tqfp x32 as7c33128pfs32a- 200tqi as7c33128pfs32a- 183tqi as7c33128pfs32a- 166tqi as7c33128pfs32a- 133tqi as7c33128pfs32a- 100tqi tqfp x36 as7c33128pfs36a- 200tqc as7c33128pfs36a- 183tqc as7c33128pfs36a- 166tqc as7c33128pfs36a- 133tqc as7c33128pfs36a- 100tqc tqfp x36 as7c33128pfs36a- 200tqi as7c33128pfs36a- 183tqi as7c33128pfs36a- 166tqi as7c33128pfs36a- 133tqi as7c33128pfs36a- 100tqi part numbering guide as7c 33 128 pf s 32/36 a ?xxx tq c/i 1 23 4 5 6789 10

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